1. Field of the Invention
The present invention relates to a semiconductor integrated circuit that constitutes a charge pump circuit which uses a predetermined power-supply voltage and responds to a clock signal to provide an internal voltage different from the power-supply voltage.
2. Description of the Prior Art
FIG. 11 depicts in block form the configuration of a conventional substrate bias circuit (a VBB circuit). Reference numeral 1 denotes a detector that detects a negative internal voltage VBB for supply to a peripheral circuit, a device substrate, a well (not shown) and so forth; 2 denotes a ring oscillator for actuation use that generates a clock signal for actuation use; 3 denotes a ring oscillator for standby use that generates a clock signal for standby use; 4 denotes a charge pump circuit for actuation use that responds to the clock signal for actuation use to provide the internal voltage VBB during actuation; and 5 denotes a charge pump circuit for standby use that responds to the clock signal for standby use to provide the internal voltage during standby.
The circuit configuration of the charge pump circuit falls into two: a single boost type and a double boost type. The single boost type has the advantages over the double boost type that it does not occupy much space and hence is space-saving and that its simple circuit configuration provides increased reliability and yield. However, the single boost type has a drawback that a drop in the power-supply voltage leads to insufficient supply of the internal voltage VBB.
On the other hand, the double boost type has the advantage that the internal voltage VBB can be supplied sufficiently even if the power-supply voltage is low to some extent, but has the defects that it occupy much space and hence is space-consuming and that its complicated circuit configuration is likely to affect reliability and yield; furthermore, since the power-supply, voltage cannot be much raised because too high a supply voltage would break down transistors of the double boost part, it may sometimes be necessary that the potential after lowering the power-supply voltage by an internal step-down circuit be used as the power supply for the charge pump circuit.
For the reasons given above, it is common practice in the art, in the case of mounting the substrate bias circuit on a chip, to design the semiconductor integrated circuit using either one of the single and double boost type charge pump circuits to meet specifications required.
FIG. 12 is a diagram depicting an example of a conventional semiconductor integrated circuit configuration, which uses the single boost type charge pump circuit. The double boost type charge pump circuit differs from the single boost type in the part surrounded by the broken lines.
The operation of the charge pump circuit shown in FIG. 12 will be described below. Assume that initial values of the potentials of nodes A to F are zero.
(1) Upon the input being switched from 0 to the power-supply voltage Vcc, the potentials of the nodes A and B change from 0 to Vcc, but the node C remains at zero potential. The potentials of the nodes D and E naturally ought to change by +Vcc since they are connected to the nodes A and B via capacitors C1 and C2, respectively, but since transistors Q4 and Q5 are in the ON state, the potentials of the nodes D and E stay low or zero until the transistors Q4 and Q5 turns OFF.
(2) Next, upon the input being switched from Vcc to 0, the potential of the node C changes from 0 to Vcc accordingly. The potential of the node F ought to change by +Vcc correspondingly, but since a transistor Q1 turns ON, the node F remains at zero potential until the transistor Q1 turns OFF. The potential of the node F at this time reaches a threshold value Vth of the transistor Q1, and consequently the transistors Q4 and Q5 turn OFF.
(3) Then, the potential of the node A changes Vcc to 0, and the potential of the node D drops by xe2x88x92Vcc accordingly.
(4) Then, the potential of the node B changes from Vcc to 0, and the potential of the node E changes to xe2x88x92Vcc, with the result that a transistor Q6 turns ON, permitting the passage therthrough of a negative potential from the node D as the internal voltage VBB.
(5) Then, upon the input being switched from 0 to Vcc, the potential of the node B changes from 0 to Vcc. Since the potential of the node E changes to +Vcc correspondingly, the transistor Q6 turns OFF, inhibiting the supply of the internal voltage VBB.
(6) Then, the potential of the node C changes from Vcc to 0, and the potential of the node F changes to xe2x88x92Vcc correspondingly. As a result, the transistors Q4 and Q5 turn ON, reducing the potentials of the nodes D and E down to zero.
(7) Then, the potential of the node A changes from 0 to Vcc, but since the transistor Q4 is in the ON state, node D remains at zero potential.
(8) By repeating steps (2) to (7), the potential of the internal voltage VBB is made to gradually go negative. FIG. 13 shows the general outlines of the timing when the steady state is reached after the repetition of the above steps.
FIG. 14 depicts an example of only a double boost part of the double boost type charge pump circuit in the configuration of the conventional semiconductor integrated circuit. The substitution of this circuit for the broken line part in FIG. 12 provides the double boost type charge pump circuit. That is, the output of the circuit depicted in FIG. 14 is connected to the node E in FIG. 12, through which it is connected to the gate of the transistor Q6 that supplies the internal voltage VBB.
Next, the operation of the semiconductor integrated circuit of FIG. 14 will be described below.
Assuming that the input is the power-supply voltage Vcc in the initial state, nodes G and I are both at zero potential and a node H is at potential Vcc. At this time, although the node G is at zero potential, the potential of a node J does not go zero correspondingly but becomes Vccxe2x88x92Vth since a transistor Q7 turns ON, where Vth is the threshold value of the transistor Q7. Since the potential of the node H is Vcc, the potential of a node K becomes Vcc. Since the node I is at zero potential, a transistor Q9 turns ON and a transistor Q10 OFF, and consequently the potential of a node L becomes Vcc.
(2) Then, when the input goes zero, the potential of the node I changes to Vcc, turning OFF the transistor Q9 and ON the transistor Q10. Hence, the potential of the node L goes zero.
(3) Next, the potential of the node G changes to Vcc and the potential of the node J changes to Vcc+2Vth accordingly.
(4) Furthermore, the potential of the node H goes zero, but the potential of the node K does not go zero and remains at Vcc since the transistor Q8 is ON.
(5) Next, when the input becomes Vcc, the potential of the node I goes zero, turning ON the transistor Q9 and OFF the transistor Q10. In consequence, the node L is connected to the node K, and hence the potential of the former changes to Vcc.
(6) Then, the potential of the node G goes to zero, and the potential of the node J changes to Vccxe2x88x92Vth accordingly.
(7) Further, the potential of the node H changes to Vcc, and the potentials of the nodes K and L both change to 2Vcc.
FIG. 15 shows the general outlines of timing when the double boost part is in the steady state. The node L and the output in FIG. 14 correspond to the nodes B and E in FIG. 12, respectively. The potentials of the nodes B and E in FIG. 12 are Vcc, whereas the potentials of the node L and the output in FIG. 14 are twice (2Vcc) higher than the power-supply voltage Vcc; therefore, the substrate bias circuit using the FIG. 12 circuit is called the single boost type and the substrate bias circuit using the FIG. 14 circuit is called the double boost type. In the double boost type circuit the potential difference between the gate and source of the transistor Q6 is larger than in the single boost type circuit, providing increased capability of supplying the internal voltage VBB.
As the working voltage lowers with the recent progress toward microminiaturization. The use of the single boost type substrate bias circuit encounters difficulties in supplying the internal voltage VBB. On the other hand, the use of the double boost type substrate bias circuit raises the potentials of the nodes K and L in the double boost part up to 2Vcc, incurring the possibility of breaking down gate oxide films of the transistors of the double boost part in the charge pump circuit.
It is therefore an object of the present invention to provide a semiconductor integrated circuit that is designed for higher reliability by holding the nodes K and L of the double boost part at potentials below 2Vcc to prevent breakdown of the gate oxide films of the transistors and for the use of the power-supply voltage Vcc over a wide voltage range.
According to an aspect of the present invention, there is provided a semiconductor integrated circuit that constitutes a charge pump circuit which uses a predetermined power-supply voltage and responds to a clock signal to provide an internal voltage different from the power-supply voltage, wherein the amplitude of a repetitive pulse, which is output from a double boost part, is made less than twice that of the power-supply voltage.
According to another aspect of the present invention, a first capacitor is connected to the double boost part, and the amplitude of the repetitive pulse from the double boost part is made less than twice that of the power-supply voltage through utilization of charge and discharge of the first capacitor by the clock signal.
According to another aspect of the present invention, the first capacitor is connected between the source of a p-channel transistor, which forms an inverter at the preceding stage of a second capacitor connected to the gate of the first transistor, and the ground.
According to another aspect of the present invention, the first capacitor is connected between the preceding stage of the second capacitor connected to the gate of the first transistor and the ground.
According to another aspect of the present invention, a plurality of first capacitors are connected to the double boost part via a plurality of fuses for laser trimming, and the amplitude of the repetitive pulse from the double boost part is made less than twice that of the power-supply voltage through utilization of charge and discharge of the plurality of first capacitors by the clock signal.
According to another aspect of the present invention, a plurality of first capacitors are connected to the double boost part via a plurality of transfer gates that are turned ON and OFF by predetermined control signals, and the amplitude of the repetitive pulse from the double boost part is made less than twice that of the power-supply voltage through utilization of charge and discharge of the plurality of first capacitors by the clock signal.
According to another aspect of the present invention, clamping circuits by a plurality of second transistors are connected to the double boost part, and the amplitude of the repetitive pulse from the double boost part is made less than twice that of the power-supply voltage.
According to another aspect of the present invention, the plurality of second transistors are connected between a p-channel transistor, which forms an inverter at the preceding stage of the second capacitor connected to the gate of the first transistor, and the power supply.
According to another aspect of the present invention, the plurality of second transistors are connected between the preceding stage of the second capacitor connected to the gate of the first transistor and the ground.
According to another aspect of the present invention, a second transistor is connected to the double boost part, and the amplitude of the repetitive pulse from the double boost part is made less than twice that of the power-supply voltage by controlling the second transistor with a predetermined control signal.
According to another aspect of the present invention, the second transistor is connected between the source of the p-channel transistor, which forms an inverter at the preceding stage of the second capacitor connected to the gate of the first transistor, and the ground.
According to another aspect of the present invention, the second transistor is connected between the preceding stage of the second capacitor connected to the gate of the first transistor and the ground.
According to another aspect of the present invention, a voltage drop is caused by a through current at the time of the ON/OFF operation of an inverter in the double boost part by the clock signal, by which the amplitude of the repetitive pulse from the double boost part is made less than twice that of the power-supply voltage.
According to another aspect of the present invention, a third transistor connected between the power supply and the inverter is provided in the double boost part, and a voltage drop is caused in the third transistor by a through current at the time of ON/OFF operation of the inverter by the clock signal.
According to another aspect of the present invention, the second transistor is connected to the double boost part, and the amplitude of the repetitive pulse from the double boost part is made less than twice that of the power-supply voltage by a voltage drop of the second transistor.
According to still another aspect of the present invention, the third transistor provided in the double boost part is connected to the power supply, and the second transistor is connected between the p-channel transistor, which forms an inverter at the preceding stage of the second capacitor connected to the gate of the first transistor, and the third transistor.